This invention relates to a conductive pattern for electric test of semiconductor chips, and more particularly to a check pattern used in aligning probes with probing pads during wafer probing.
In general, in the final stage of manufacturing semiconductor devices, for example, when the wafer process is completed, various electric tests for determining pass/fail of semiconductor chips are performed by contacting the probes of a testing apparatus to probing pads provided in the periphery of a semiconductor chip formed on a wafer.
Aligning the probes with the pads is performed by observing the relationship of their positions with a microscope disposed above the pads of the semiconductor chip.
In the alignment, if an area having the probes is small, the magnification of the microscope for observation is increased to obtain the necessary accuracy of alignment. However, there is the tendency for the area having the probes (i.e. the alignment determination area) to become larger because of the increase in semiconductor chip sizes for semiconductor devices because of the realization of high performance and simultaneous probing for multiple chips.
This tendency for the probing area to become larger results in the problem that the alignment of the probe with pads becomes difficult. This is because if the magnification of the microscope is increased, the entire probing area cannot be observed in the field of view of the microscope, and only partial observation is possible. On the other hand, if the magnification of the microscope is decreased in order to observe the entire probing area, it becomes difficult to obtain satisfactory accuracy for aligning the probes with the pads.
Because of the alignment determining area becoming larger due to increase in chip sizes and multiple probing as described above, there arise problems of the high magnification of the microscope resulting in difficulty of performing alignment, and of low magnification of the microscope resulting in lowered accuracy of alignment.